ASIC / VLSI ENGINEERS – STA / Physical Design / Design Verification
3 outstanding, full-time positions have become available; a) STA Engineer, b) Physical Design Engineer, and c) Design Verification Engineer; in the Silicon Valley area for individuals with a minimum of 4+ years of experience in ASIC / VLSI design engineering within advanced semiconductor environments. This opportunity is with a well-established engineering services firm supporting some of the most innovative product companies in the industry.
Each position requires the ability to work On-Site at individual client facilities in the South Bay area.
These are full-time, permanent positions working on advanced chip development projects with leading technology companies. This position offers competitive compensation up to $225K per year, along with a comprehensive benefits package and other perks.
All candidates MUST have the following experiences to qualify for consideration
• Strong experience working with RTL design environments & ASIC development flows
• Experience working within advanced process technologies (28nm & below preferred)
• Strong scripting experience with Python, Tcl, Perl, or similar
• Strong understanding of timing analysis, digital logic design, & semiconductor design flows
Candidates should have strong experience in ONE of the following areas
Static Timing Analysis Engineer - STA Engineer
• RTL synthesis and timing analysis
• Static timing analysis using tools such as Synopsys PrimeTime or Cadence Tempus
• Timing closure methodologies and optimization
• Experience working with Verilog or VHDL based designs
Physical Design Engineer - PD Engineer
• ASIC physical design implementation including floorplanning, placement, and clock tree synthesis (CTS)
• Timing closure and signal integrity analysis
• Power grid design, IR drop analysis, and low power methodologies
• Experience with physical verification and advanced node implementation
Design Verification Engineer– DV Engineer
• ASIC / RTL design verification across the full verification lifecycle
• Experience developing testbenches using SystemVerilog and UVM methodology
• Debugging simulations and verification environments
• Experience with VCS or similar simulators
• Familiarity with common protocols such as AXI or AHB
If interested and QUALIFIED, please send resume in Microsoft Word format to: krissid@etechhi.com
Etech Hi, Inc. is an equal opportunity employer/staffing firm and we are committed to providing a workplace free from harassment and discrimination. We celebrate the unique differences of our employees and candidates because that is what drives curiosity, innovation, and the success of our business. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, gender identity or expression, age, marital status, veteran status, disability status, pregnancy, parental status, genetic information, political affiliation, or any other status protected by the laws or regulations in the locations where we operate.
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